CHI TIẾT CÔNG VIỆC
- Physical Design (Back-end): Drive and execute the complete back-end design flow, ensuring a seamless transition from Netlist to GDSII.
- SoC Place & Route (P&R): Lead SoC P&R activities, including Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing.
- Timing Closure: Take ownership of Timing Closure to ensure the design meets all performance targets and constraints.
- Physical Verification (PV): Perform rigorous Signoff Physical Verification, including Design Rule Check (DRC) and Layout vs. Schematic (LVS).
- Power Analysis: Execute Signoff-level Power Estimation, Analysis, and Verification to optimize energy efficiency.
- PSI Analysis: Conduct comprehensive On-Chip Power-Signal Integrity (PSI) analysis to ensure silicon reliability.
- Hardening: Manage and optimize CPU/GPU Hardening processes to achieve high-performance physical implementation.
YÊU CẦU CÔNG VIỆC
- Education: Bachelor’s Degree or higher in Electrical Engineering, Computer Engineering, or a related technical field.
- Experience: Minimum of 3 years of hands-on experience in Physical Implementation and Back-end design.
- Core Knowledge: Deep expertise in ASIC design flows, advanced P&R methodologies, and Physical Verification (PV) protocols.
- Power Design: Proficient in Low Power Design techniques, Multi-power domain management, and Unified Power Format (UPF).
- Scripting: Strong ability to use TCL or Python scripting for design automation and flow optimization.
- Technical Proficiency: Solid, hands-on experience in Floorplanning, P&R, Signoff DRC/LVS, and CPU/GPU Hardening.
PREFERRED QUALIFICATIONS
- Full-chip Expertise: Extensive experience in Full-chip Physical Design, Implementation, and Verification for complex, large-scale SoCs.
- Advanced Automation: Advanced scripting capabilities (TCL, Python) with the ability to develop and optimize proprietary implementation flows.
- High-Speed Analysis: Specialized experience in Off-chip PSI analysis for high-speed and high-power silicon.
- Proven Track Record: A strong history of successful high-performance CPU/GPU Hardening and tape-outs.
QUYỀN LỢI
1. BE A CHIP MAKER - NOT JUST A CODER
- Full-Flow Ownership: Take ownership of the entire design lifecycle. You will not just write code; you will work closely with Architecture, DV, PD, DFT, and Power teams to bring a Large-Scale SoC from concept to Tape-out.
- Cutting-Edge Tech: Work on advanced ASIC IP-based architectures for AI & Smart Camera applications. Handle sophisticated sub-systems and internal/external IP integration.
- Impactful Work: Develop methodology, flows, and checks that ensure our chips deliver the highest quality and efficiency (TOPs/Watt).
2. TOP-TIER BENEFITS & CARE
- Competitive Package: Attractive salary + 13th-month salary + Performance-based bonuses.
- Premium Healthcare: Exclusive FPT Care insurance package (covering you and your family) with access to top international hospitals. Annual high-quality health check-ups.
- Work-Life Balance: Full compliance with Labor Law, generous leave policies, and care for employees' spiritual lives.
3. DYNAMIC ENVIRONMENT & GROWTH
- Vibrant Culture: Join a friendly, open team with the unique "STCo" culture. Enjoy exciting activities: Teambuilding, Company Trips, Talent Shows (Sao Choi), Festivals, and more!
- Career Path: Clear roadmap for promotion and technical development. Work with modern facilities and high-quality equipment.
- Exclusive Perks: Special discounts on FPT Telecom & FPT ecosystem services.
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