CHI TIẾT CÔNG VIỆC
- NPU Micro-architecture: Define and implement micro-architecture for high-performance AI acceleration cores, including Matrix Multiplication Engines (GEMM), Vector Processors, and Systolic Arrays.
- RTL Development: Write high-quality, synthesizable RTL code (Verilog/SystemVerilog) for complex AI sub-systems and specialized IP blocks.
- Dataflow & Memory Optimization: Design efficient on-chip memory hierarchies (SRAM/Cache) and dataflow controllers to minimize latency and optimize data movement for AI workloads.
- SoC Integration: Integrate NPU IPs into the top-level SoC, managing complex Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and high-speed bus interconnects.
- PPA Optimization: Drive Logic Synthesis and collaborate closely with the Physical Design team to achieve aggressive PPA (Power, Performance, Area) targets and ensure timing closure.
- Quality Assurance: Perform rigorous Lint, CDC, and RDC checks. Support the Verification team in debugging and achieving 100% code/functional coverage.
- Modeling Collaboration: Partner with AI Compiler and Architecture teams to validate bit-accurate hardware models against algorithmic C/C++ reference models.
YÊU CẦU CÔNG VIỆC
- Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience: Minimum 3+ years of professional experience in ASIC/SoC RTL Design.
- Technical Skills:
- Expertise in SystemVerilog/Verilog and digital logic design.
- Deep understanding of AMBA protocols (AXI, AHB, APB) and high-speed interconnects.
- Strong knowledge of Fixed-point arithmetic and hardware architectures for parallel processing (SIMD, DSP).
- Experience with low-power design techniques (UPF/CPF, Clock Gating, Power Gating).
- EDA Tools: Proficient with industry-standard tools: Synopsys (Design Compiler, SpyGlass, PrimeTime, VCS) or Cadence equivalents.
- Preferred Qualifications:
- Prior experience in designing NPU, GPU, DSP, or high-performance compute accelerators.
- Familiarity with AI frameworks (TensorFlow, PyTorch) or Quantization techniques (INT8, FP16).
- Experience with high-speed interfaces like PCIe, DDR, or HBM.
QUYỀN LỢI
1. BE A CHIP MAKER – Shape the Future of AI Silicon
- Full-Flow Ownership: Experience the complete silicon lifecycle. You won't just write code; you will drive the design from initial concept and architecture to Tape-out.
- Cutting-Edge Tech: Work on advanced NPU architectures for Smart Cameras, Edge AI, and Autonomous systems.
- High Impact: Develop the methodologies and IPs that define our chip’s efficiency (TOPS/Watt) and market competitiveness.
2. TOP-TIER BENEFITS & CARE
- Competitive Package: Attractive base salary + 13th-month salary + performance-based bonuses.
- Premium Healthcare: Exclusive FPT Care insurance package for you and your family, providing access to top-tier international hospitals.
- Well-being: Annual high-quality health check-ups and a supportive work-life balance environment.
3. DYNAMIC ENVIRONMENT & GROWTH
- Vibrant Culture: Join an open, innovative team with the unique "STCo" culture. Engage in teambuilding, company trips, and large-scale festivals (Sao Choi, Talent Shows).
- Career Roadmap: Clear paths for technical specialization (Specialist/Principal Engineer) or leadership roles.
- Exclusive Perks: Special discounts across the FPT ecosystem (FPT Telecom, FPT Retail, FPT Education).
THÔNG TIN THAM KHẢO
-
Tìm hiểu về FPT Telecom
tại đây
-
Quy trình tuyển dụng tại FPT Telecom
tại đây
