CHI TIẾT CÔNG VIỆC

• Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes

• Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution 

• Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs

• Define and implement schemes, including semi-custom placement and routing, to improve performance and power

• Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle resolve congestion/timing issues and implement functional ECO’s

• Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality

• Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions

YÊU CẦU CÔNG VIỆC

• 5+ years of experience in interpersonal, teamwork, communication skills and experience interfacing with cross-functional teams, IP, and EDA vendors

• Knowledge of RTL2GDSII flow and design tape-outs in 16nm/14nm or below process technologies

• Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions

• Experience in full chip floor planning, partitioning, budgeting, and power grid planning

• Experience with low power implementation, power gating, multiple voltage rails, UPF/CPF knowledge

• Experience in planning, implementing, and analyzing high-speed clock distribution networks. Experience with alternate strategies for clock distribution, including standard trees, mesh, H-Tree, and clock power reduction techniques

• Experience in the physical design of data-path intensive designs

• Experience in validating Power Distribution Network (PDN), IR/EM, Thermals for 3D-IC

• Experience with EDA tools like DC/Genus, Innovus/ICC2 Programming/scripting skills: TCL, Python, Perl or Shell 

QUYỀN LỢI

• This role will give you ownership of all aspects of design and development of large SoCs, SoC blocks and sub-systems. Handle internal/external IP integration and build sophisticated sub-systems.
• Work on cutting-edge projects in ASIC design and verification. 
• Work closely with Chip Architecture, Design Verification, Physical Design, DFT and power teams to achieve SoC tapeout goals on schedule.
• Collaboration with a dynamic and experienced team of experts.
• Develop and maintain methodology/flows/checks for your design.
• Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process.

THÔNG TIN THAM KHẢO

• Tìm hiểu về FPT Telecom tại đây
• Quy trình tuyển dụng tại FPT Telecom tại đây