CHI TIẾT CÔNG VIỆC
We are seeking a versatile Senior IC Design Engineer with deep expertise in both RTL Design and Design Verification (DV). In this role, you will be a key architect of our custom AI Accelerator (NPU) and SoC subsystems. You will be responsible for the entire logic lifecycle - from micro-architecture definition and RTL coding to building advanced UVM environments to ensure first-pass silicon success.
Key Responsibilities:
1. RTL Design & Integration:
- Micro-Architecture: Transform high-level AI algorithm requirements into detailed hardware micro-architecture specifications.
- RTL Coding: Develop high-performance, area-efficient logic using Verilog/SystemVerilog for AI kernels, memory controllers, and high-speed interconnects.
- SoC Integration: Integrate internal and third-party IPs (NPU, ISP, PCIe, DDR) into the SoC fabric.
- Design Implementation: Perform Linting, CDC (Clock Domain Crossing) analysis, and initial Logic Synthesis to ensure design "routability" and timing closure.
- Low Power: Implement low-power design techniques (Clock gating, power domains) using UPF/CPF.
2. Design Verification (DV):
- Verification Strategy: Define comprehensive verification plans based on design specs.
- UVM Benchmarking: Build and maintain scalable, constrained-random verification environments using SystemVerilog and UVM.
- Debugging: Lead the debug efforts for complex RTL/testbench failures at both block and SoC levels.
- Coverage Closure: Drive functional and code coverage to 100%, ensuring all corner cases of the AI Chip are validated.
- Gate-Level Simulation (GLS): Execute GLS to verify timing and reset behaviors post-synthesis.
YÊU CẦU CÔNG VIỆC
- Experience: 5+ years of experience in front-end IC Design (RTL & DV).
- Languages: Expert in Verilog, SystemVerilog, and UVM.
- Protocol Knowledge: Strong understanding of AMBA protocols (AXI, CHI, ACE, AHB, APB).
- EDA Tools: Proficient with Cadence (Xcelium, Genus, JasperGold) or Synopsys (VCS, Design Compiler, SpyGlass) toolchains.
- Scripting: Ability to automate flows using Python, Tcl, or Perl.
- Academic: Degree in Electronics, Telecommunications, or Computer Engineering.
Preferred Qualifications:
- Previous experience in AI Accelerator (NPU/TPU) or DSP design.
- Familiarity with Automotive Functional Safety (ISO 26262) standards.
- Experience with Formal Verification or Hardware Emulation (Palladium/Zebu).
QUYỀN LỢI
1. BE A CHIP MAKER - NOT JUST A CODER
- Full-Flow Ownership: Take ownership of the entire design lifecycle. You will not just write code; you will work closely with Architecture, DV, PD, DFT, and Power teams to bring a Large-Scale SoC from concept to Tape-out.
- Cutting-Edge Tech: Work on advanced ASIC IP-based architectures for AI & Smart Camera applications. Handle sophisticated sub-systems and internal/external IP integration.
- Impactful Work: Develop methodology, flows, and checks that ensure our chips deliver the highest quality and efficiency (TOPs/Watt).
2. TOP-TIER BENEFITS & CARE
- Competitive Package: Attractive salary + 13th-month salary + Performance-based bonuses.
- Premium Healthcare: Exclusive FPT Care insurance package (covering you and your family) with access to top international hospitals. Annual high-quality health check-ups.
- Work-Life Balance: Full compliance with Labor Law, generous leave policies, and care for employees' spiritual lives.
3. DYNAMIC ENVIRONMENT & GROWTH
- Vibrant Culture: Join a friendly, open team with the unique "STCo" culture. Enjoy exciting activities: Teambuilding, Company Trips, Talent Shows (Sao Choi), Festivals, and more!
- Career Path: Clear roadmap for promotion and technical development. Work with modern facilities and high-quality equipment.
- Exclusive Perks: Special discounts on FPT Telecom & FPT ecosystem services.
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