CHI TIẾT CÔNG VIỆC
ROLE OVERVIEW
FPT Telecom is pioneering the development of custom AI System-on-Chip (SoC) to power our next-generation Smart Camera and IoT ecosystems. We are seeking core IC Design experts to turn ambitious AI algorithms into silicon reality. In this role, you won't just "design chips"—you will be a founding architect of FPT’s semiconductor legacy, ensuring first-pass silicon success for our high-performance AI hardware.
DETAILED ROLES & RESPONSIBILITIES
1. Senior RTL Design Engineer
- Micro-Architecture: Translate complex AI algorithms (CNN, Transformer) into detailed hardware micro-architecture specifications, optimizing for MAC units and memory hierarchy (Cache/Scratchpad).
- RTL Coding & Optimization: Develop high-performance logic using SystemVerilog/Verilog, focusing on PPA (Power-Performance-Area) optimization for AI Kernels and High-speed Interconnects.
- SoC Integration: Integrate complex SoC subsystems including NPUs, ISPs, DDR5/LPDDR4, PCIe, and Network-on-Chip (NoC) fabrics.
- Design Implementation: Execute Lint, CDC (Clock Domain Crossing), RDC, and initial Logic Synthesis to ensure "routability" and timing-clean handoffs to the Physical Design team.
2. Senior Design Verification (DV) Engineer
- Verification Strategy: Define comprehensive test plans covering functional specs and critical "corner cases" unique to AI architectures.
- Advanced UVM Environment: Architect and maintain scalable, constrained-random, OOP-based testbenches using SystemVerilog/UVM from block-level to full-chip.
- C/C++ Modeling: Collaborate on building Golden Reference Models in C/C++/SystemC to validate RTL data integrity and algorithmic accuracy.
- Coverage & Performance Closure: Drive Functional and Code Coverage to 100%. Perform Performance Verification to ensure the chip meets target TOPS (Tera Operations Per Second).
- Post-Synthesis Verification: Execute Gate-Level Simulation (GLS) to verify timing and reset behaviors post-synthesis.
YÊU CẦU CÔNG VIỆC
- Experience: Minimum 5+ years of proven experience in Front-end IC Design/Verification. Must have participated in at least one successful Tape-out project.
- Technical Stack: Expert in Verilog and SystemVerilog. Advanced mastery of UVM is mandatory for the DV role.
- Systems Knowledge: Deep understanding of AMBA protocols (AXI, CHI, ACE, AHB, APB). Solid grasp of computer architecture and parallel processing.
- EDA Toolchains: Proficiency in industry-standard tools from Cadence (Xcelium, Genus, JasperGold) or Synopsys (VCS, Design Compiler, SpyGlass).
- Scripting: Ability to automate design/verification flows using Python, Tcl, or Perl.
- Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
PREFERRED QUALIFICATIONS
- Prior experience in designing AI Accelerators (NPU/TPU/GPU) or DSPs.
- Hands-on experience with Formal Verification or Hardware Emulation systems (Palladium/Zebu).
- Familiarity with AI data formats (INT8, FP16, Bfloat16) and CI/CD workflows for hardware.
- Strong leadership or mentoring skills to guide junior/fresher engineers.
- Low-Power Design: Experience in implementing advanced power-saving techniques (Multi-voltage domains, Power gating) using UPF/CPF formats.
QUYỀN LỢI
1. BE A CHIP MAKER - NOT JUST A CODER
- Full-Flow Ownership: Take ownership of the entire design lifecycle. You will not just write code; you will work closely with Architecture, DV, PD, DFT, and Power teams to bring a Large-Scale SoC from concept to Tape-out.
- Cutting-Edge Tech: Work on advanced ASIC IP-based architectures for AI & Smart Camera applications. Handle sophisticated sub-systems and internal/external IP integration.
- Impactful Work: Develop methodology, flows, and checks that ensure our chips deliver the highest quality and efficiency (TOPs/Watt).
2. TOP-TIER BENEFITS & CARE
- Competitive Package: Attractive salary + 13th-month salary + Performance-based bonuses.
- Premium Healthcare: Exclusive FPT Care insurance package (covering you and your family) with access to top international hospitals. Annual high-quality health check-ups.
- Work-Life Balance: Full compliance with Labor Law, generous leave policies, and care for employees' spiritual lives.
3. DYNAMIC ENVIRONMENT & GROWTH
- Vibrant Culture: Join a friendly, open team with the unique "STCo" culture. Enjoy exciting activities: Teambuilding, Company Trips, Talent Shows (Sao Choi), Festivals, and more!
- Career Path: Clear roadmap for promotion and technical development. Work with modern facilities and high-quality equipment.
- Exclusive Perks: Special discounts on FPT Telecom & FPT ecosystem services.
THÔNG TIN THAM KHẢO
-
Tìm hiểu về FPT Telecom
tại đây
-
Quy trình tuyển dụng tại FPT Telecom
tại đây
